AESelerator: Advanced Encryption Standard Cryptographic Accelerator


Overview

Clock signals in the AESelerator chip

Clock signals in the AESelerator chip

The goal of this project is to build a hardware-based encryption unit that implements the Advanced Encryption Standard (AES). The AESelerator encryption unit will be able to communicate via a network interface to send and receive data in TCP/IP format. Carrying out the encryption in hardware is faster than doing so in software.

We designed in Verilog hardware design language, and used Synopsys VCS, LEDA, Design Compiler, and IC Compiler.

Project Documentation

AESelerator Project Documentation

Source Code Excerpt

AESelerator.v

Code Activity

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