/**Columbia University EECS 4340 Computer Hardware Design**/
/**Fall 2010 Final Project**/
/**Scott Rogowski, Hsin-Tien Shen, Yipeng Huang**/
/**AESelerator**/

/*
This project will implement a hardware-based encryption unit that implements the Advanced
Encryption Standard (AES). The AESelerator encryption unit will be able to communicate via a
network interface to send and receive data in TCP/IP format.

Encryption methods allow sensitive data to be sent over a network connection securely. The
sending party and the receiving share an encryption key that is communicated separately from the
data itself. If encrypted data is intercepted during transmission, the intercepting party cannot
decrypt and gain access to the data without access to the key.

The Advanced Encryption Standard (AES) is a symmetric-key encryption standard adopted by the
US government for all governmental encryption requirement. The algorithm was selected for its
simplicity, robustness, and speed. A detailed description of the algorithm can be found in the
Federal Information Processing Standards Publication 197.
*/

module AESelerator (
	/*AUTOARG*/
   // Outputs
   ready_o, flit_o,
   // Inputs
   clk, reset, flit_valid_i, config_i, flit_i 
   );

//Standard inputs
input clk, reset;

//Inputs
input flit_valid_i;
input [7:0] config_i;
input [3:0][7:0] flit_i;

//Outputs
output ready_o;
output [3:0][7:0] flit_o;



//IO for intermediate testing purposes
/*input [3:0][7:0] key0_i, key1_i, key2_i, key3_i;
input [3:0][7:0] data0_i, data1_i, data2_i, data3_i, data4_i, data5_i, data6_i, data7_i;
output [3:0][7:0] data0_o, data1_o, data2_o, data3_o, data4_o, data5_o, data6_o, data7_o;*/


//Reverse the flit lines because verilog reads back to front and C reads front to back
/*
wire [3:0][31:0] key_i_mid;
wire [3:0][31:0] data_i_mid_0;
wire [3:0][31:0] data_i_mid_1;
*/
wire [3:0][31:0] data_o_mid_0;
wire [3:0][31:0] data_o_mid_1;
/*
assign key_i_mid[3] = key0_i;
assign key_i_mid[2] = key1_i;
assign key_i_mid[1] = key2_i;
assign key_i_mid[0] = key3_i;

assign data_i_mid_0[3] = data0_i;
assign data_i_mid_0[2] = data1_i;
assign data_i_mid_0[1] = data2_i;
assign data_i_mid_0[0] = data3_i;
assign data_i_mid_1[3] = data4_i;
assign data_i_mid_1[2] = data5_i;
assign data_i_mid_1[1] = data6_i;
assign data_i_mid_1[0] = data7_i;
*/
/*
assign data0_o = data_o_mid_0[3];
assign data1_o = data_o_mid_0[2];
assign data2_o = data_o_mid_0[1];
assign data3_o = data_o_mid_0[0];
assign data4_o = data_o_mid_1[3];
assign data5_o = data_o_mid_1[2];
assign data6_o = data_o_mid_1[1];
assign data7_o = data_o_mid_1[0];
*/
//Finally, the main modules
wire error, encrypt_begin;
wire [3:0][31:0] key;
wire [4:0][31:0] header;
wire [3:0][31:0] data0;
wire [3:0][31:0] data1;
Inputter inputter (
	//ouptuts
	.ready_o(ready_o),
	.error(error),
	.key(key),
	.header(header),
	.data0(data0),
	.data1(data1),
	.encrypt_begin(encrypt_begin),
	//inputs
	.clk(clk),
	.enable(1'b1),
	.reset(reset),
	.config_i(config_i),
	.flit_i(flit_i),
	.flit_valid_i(flit_valid_i)
	);

wire i9, i10, i11, i12, i13, i14, i15, i20, i21;
wire [4:0] count;
Counter counter (
	// Outputs
	.count(count),
	.i9(i9),
	.i10(i10),
	.i11(i11),
	.i12(i12),
	.i13(i13),
	.i14(i14),
	.i15(i15),
	.i20(i20),
	.i21(i21),
	// Inputs
	.clk(clk),
	.reset(reset || encrypt_begin),
	.enable(1'b1)
	);

wire [3:0][31:0] round_key;
RoundKeyGenerator round_key_generator (
	// Outputs
	.key_out(round_key),
	// Inputs
	.clk(clk),
	.reset(reset),
	.encrypt_begin(encrypt_begin),
	.counter(count),
	.key_in(key)
	);

Encrypter encrypter0 (
	//Outputs
	.data_out(data_o_mid_0),
	
	//Inputs
	.clk(clk),
	.reset(reset),
	.encrypt_begin(encrypt_begin),
	.data_in(data0),
	.key_in(round_key),
	.i10(i10),
	.i11(i11)
	);
	
Encrypter encrypter1 (
	//Outputs
	.data_out(data_o_mid_1),
	
	//Inputs
	.clk(clk),
	.reset(reset),
	.encrypt_begin(encrypt_begin),
	.data_in(data1),
	.key_in(round_key),
	.i10(i10),
	.i11(i11)
	);

wire [255:0] ciphertext;
assign ciphertext = {data_o_mid_1, data_o_mid_0};
Outputter outputter (
	//Outputs
	.flit_o(flit_o),
	//Inputs
	.clk(clk),
	.enable_write(encrypt_begin),
	.reset(reset),
	.error(error),
	.header(header),
	.i11(i11),
	.i13(i13), 
	.i14(i14),
	.ciphertext(ciphertext)
	);

endmodule