The goal of this project is to build a hardware-based encryption unit that implements the Advanced Encryption Standard (AES). The AESelerator encryption unit will be able to communicate via a network interface to send and receive data in TCP/IP format. Carrying out the encryption in hardware is faster than doing so in software.

We designed in Verilog hardware design language, and used Synopsys VCS, LEDA, Design Compiler, and IC Compiler.